Split gate flash memory cell and fabrication method thereof
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United States of America Patent
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Feb 3, 2009
Grant Date -
Apr 26, 2007
app pub date -
Mar 28, 2006
filing date -
Oct 26, 2005
priority date (Note) -
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Abstract
A split gate flash memory cell comprising a semiconductor substrate having a first insulating layer thereon and a floating gate with a first width is disclosed. The cell further comprises a second insulating layer, a control gate and a cap on the floating gate in sequence. The cap layer, the control gate and the second insulating layer have a same second width less than the first width. The cell also comprises a third insulating layer over the semiconductor substrate, the sidewalls of the control gate, the second insulating layer, the floating gate, and the first insulating layer. In addition, an erase gate formed on the third insulating layer is provided.
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