Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Dec 14, 2004
Grant Date -
Sep 5, 2002
app pub date -
Jul 16, 2001
filing date -
Mar 2, 2001
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
Structures and methods for fabricating high speed digital, analog, and combined digital/analog systems using planarized relaxed SiGe as the materials platform. The relaxed SiGe allows for a plethora of strained Si layers that possess enhanced electronic properties. By allowing the MOSFET channel to be either at the surface or buried, one can create high-speed digital and/or analog circuits. The planarization before the device epitaxial layers are deposited ensures a flat surface for state-of-the-art lithography.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully