Multiprocessor data processing system having scalable data interconnect and data routing mechanism

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United States of America Patent

PATENT NO 7308558
APP PUB NO 20050149692A1
SERIAL NO

10752959

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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The data interconnect and routing mechanism reduces data communication latency, supports dynamic route determination based upon processor activity level/traffic, and implements an architecture that supports scalable improvements in communication frequencies. In one application, a data processing system includes first and second processing books, each including at least first and second processing units. Each of the first and second processing units has a respective first output data bus. The first output data bus of the first processing unit is coupled to the second processing unit, and the first output data bus of the second processing unit is coupled to the first processing unit. At least the first processing unit of the first processing book and the second processing unit of the second processing book each have a respective second output data bus. The second output data bus of the first processing unit of the first processing book is coupled to the first processing unit of the second processor book, and the second output data bus of the second processing unit of the second processor book is coupled to the second processing unit of the first processor book.

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Patent Owner(s)

  • GOOGLE LLC

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Arimilli, Ravi Kumar Austin, TX 371 7238
Chung, Vicente Enrique Austin, TX 16 176
Joyner, Jody Bern Austin, TX 30 373
Lewis, Jerry Don Round Rock, TX 145 2407

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