Self-verification of configuration memory in programmable logic devices
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United States of America Patent
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Jul 15, 2008
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N/A
app pub date -
May 18, 2007
filing date -
Jan 13, 2005
priority date (Note) -
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Abstract
In one embodiment, a programmable logic device is provided that includes a memory having memory cells, each memory cell operable to store either a configuration bit or a RAM bit; a masking circuit operable to mask a RAM bit by providing a masking value for the masked RAM bit; an error detection circuit operable to process the configuration bits during operation of the programmable logic device using an error detection algorithm, the error detection circuit calculating a signature that includes configuration bits and masking values; and a comparator operable to compare the signature calculated by the error detection circuit with a correct signature.
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