Initialization sequencing of chiplet I/O channels within a chiplet system

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United States of America Patent

PATENT NO 11669486
SERIAL NO

17572240

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Abstract

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A system comprises an interposer including interconnect and multiple chiplets arranged on the interposer. Each chiplet includes multiple chiplet input-output (I/O) channels interconnected to I/O channels of other chiplets by the interposer; a chiplet I/O interface for the chiplet I/O channels that includes multiple interface layers; and initialization logic circuitry configured to advance initialization of the chiplet interface sequentially through the interface layers starting with a lowest interface layer.

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Patent Owner(s)

  • MICRON TECHNOLOGY INC.

International Classification(s)

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Brewer, Tony M Plano, US 161 2216
Walker, Dean E Allen, US 39 214

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