Processor performing parallel operations subject to operand register interference using operand history storage
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United States of America Patent
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Jul 16, 2002
Grant Date -
Apr 25, 2002
app pub date -
Mar 16, 1999
filing date -
Jun 29, 1998
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A register interference state where a register which is updated by a preceding instruction is used by a succeeding instruction, for example, for the generation of an operand address, is detected. When a register interference state is detected, the execution of a succeedingly fetched instruction is started by storing an operand address generated when the succeeding instruction is executed in association with the address of the succeeding instruction. The operand address is estimated which corresponds to the address of the succeedingly fetched instruction and is retrieved from the stored contents.
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