Synchronous memory bus access to storage media
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United States of America Patent
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-
Jan 3, 2023
Grant Date -
N/A
app pub date -
May 14, 2021
filing date -
Feb 5, 2018
priority date (Note) -
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Abstract
A computing system having memory components, including first memory and second memory, wherein the first memory is available to a host system for read and write access over a memory bus during one or more of a first plurality of windows. The computing system further includes a processing device, operatively coupled with the memory components, to: receive, from a driver of the host system, a request regarding a page of data stored in the second memory; responsive to the request, transfer the page from the second memory to a buffer; and write the page from the buffer to the first memory, wherein the page is written to the first memory during at least one of a second plurality of windows corresponding to a refresh timing for the memory bus, and the refresh timing is controlled at the host system.
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