Manufacturing process of a chip package structure
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United States of America Patent
Stats
-
Nov 24, 2009
Grant Date -
Oct 19, 2006
app pub date -
May 26, 2006
filing date -
Feb 11, 2003
priority date (Note) -
In Force
status (Latency Note)
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Abstract
A manufacturing process of a chip package structure is provided. The manufacturing method uses fine pitch circuit processes, such as a TFT-LCD process or an IC process, to increase layout density and shorten electrical transmission pathways so that a higher electrical performance level is attained. First, a multi-layered interconnection structure with high-density bonding pads and fine pitch circuit is formed over a hard support base plate having a large area and high degree of planarity. A die is attached to a top surface of the multi-layered interconnection structure. A plurality of opening is formed on a bottom surface of the support base plate. Contacts are positioned into the openings in the support base plate such that the contacts are electrically connected to an inner circuit within the multi-layered interconnection structure.
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