Inter-wire cavity for low capacitance

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United States of America Patent

PATENT NO 11551968
APP PUB NO 20210335655A1
SERIAL NO

17029213

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Abstract

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Various embodiments of the present disclosure are directed towards an integrated circuit (IC) in which cavities separate wires of an interconnect structure. For example, a conductive feature overlies a substrate, and an intermetal dielectric (IMD) layer overlies the conductive feature. A first wire and a second wire neighbor in the IMD layer and respectively have a first sidewall and a second sidewall that face each other while being separated from each other by the IMD layer. Further, the first wire overlies and borders the conductive feature. A first cavity and a second cavity further separate the first and second sidewalls from each other. The first cavity separates the first sidewall from the IMD layer, and the second cavity separates the second sidewall from the IMD layer. The cavities reduce parasitic capacitance between the first and second wires and hence resistance-capacitance (RC) delay that degrades IC performance.

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Patent Owner(s)

  • TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Chen, Chang-Wen Hsin-Chu, TW 10 171
Chen, Chii-Ping Hsinchu, TW 45 141
Hsueh, Hsiu-Wen Taichung, TW 28 28
Huang, Po-Hsiang Taipei, TW 142 353
Wu, Cai-Ling Hsin-Chu, TW 12 6
Yang, Jiing-Feng Zhubei, TW 18 648

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