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Abstract

A memory cell (400) for storing data on an integrated circuit. The memory cell (400) is static, nonvolatile, and reprogrammable. The layout of the memory cell is compact. In a first state, the logic output from this memory cell (400) is at about voltage level at a first conductor (505); and in a second state, the logic output is at about a voltage level at a second conductor (510). The memory cell (400) of the present invention includes a first programmable memory element (515) and a second programmable memory element (520). First programmable memory element (515) is coupled between the first conductor (505) and a sensing node (405). Second programmable memory element (520) is coupled between the sensing node (405) and the second conductor (510). In the first state, first programmable memory element (515) is not programmed, while the second programmable memory element (520) is programmed. In the second state, first programmable memory element (515) is programmed, while second programmable memory element (520) is not programmed.

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First Claim