Clock-reconvergence pessimism removal in hierarchical static timing analysis
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United States of America Patent
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Aug 19, 2014
Grant Date -
Sep 19, 2013
app pub date -
Apr 29, 2013
filing date -
Apr 27, 2011
priority date (Note) -
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Abstract
A system and a method are disclosed for performing clock re-convergence pessimism removal (CRPR) during hierarchical static timing analysis (HSTA). A clock network is divided into a plurality of blocks. A top level includes clock components not included in the plurality of blocks. Block level analysis is performed to determine timing information for each of the plurality of blocks. If available, CRPR data from top level analysis is accounted for in block level analysis. Subsequently, similar analysis is performed on components that are included in top level analysis. If available, CRPR data from bottom level analysis is accounted for in top level analysis. CRPR data can be requested during levels of analysis from the other level. These steps are repeated until analysis is complete.
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