Semiconductor device manufacturing method and mold die
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United States of America Patent
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May 6, 2003
Grant Date -
N/A
app pub date -
Dec 15, 1999
filing date -
Jul 5, 1999
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Abstract
A semiconductor device manufacturing method and a mold die that make it possible to expose the upper portions of external terminals with ease without having to implement a polishing process, are provided. The semiconductor device manufacturing method comprises a step in which external terminals are formed as bumps on a semiconductor element substrate, a step in which the semiconductor element substrate is mounted on the upper surface of a lower die of a mold die comprising an upper die and the lower die that is used to seal the semiconductor element substrate in resin, a step in which a tape is placed over the area of the upper surface of the lower die where the semiconductor element substrate is mounted and a step in which the upper die is placed in close contact with the external terminals. By employing this manufacturing method, it is possible to control the clamping force of the mold die. Thus, even when the upper die of the mold die is placed in close contact with the external terminals, deformation of the external terminals and damage to the semiconductor element do not occur. As a result, a polishing process for exposing the external terminals can be omitted and an improvement in yield is achieved.
First Claim
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- 15 United States
- 10 France
- 8 Japan
- 7 China
- 5 Korea
- 2 Other
Patent Owner(s)
- LAPIS SEMICONDUCTOR CO., LTD.
International Classification(s)
Inventor(s)
Inventor Name | Address | # of filed Patents | Total Citations |
---|---|---|---|
Iguchi, Akihisa | Tokyo, JP | 4 | 25 |
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Fee | Large entity fee | small entity fee | micro entity fee | due date |
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Fee | Large entity fee | small entity fee | micro entity fee |
---|---|---|---|
Surcharge after expiration - Late payment is unavoidable | $700.00 | $350.00 | $175.00 |
Surcharge after expiration - Late payment is unintentional | $1,640.00 | $820.00 | $410.00 |
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