Importance

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Abstract

An apparatus for compensating a locking error in a high speed memory device includes a division unit for dividing a buffered external clock signal into a first clock signal, a second clock signal, and a third clock signal having twice the low level width of the second clock signal, a selection unit for selecting one of the second clock signal and the third clock signal in response to a first control signal, a delay unit for delaying the first clock signal and gradually increasing a time delay in response to a second control signal, a unit for delaying the delayed first clock signal according to a modeling of a delay time to generate a fourth clock signal, an initial clock control unit for generating the first control signal, and a phase comparison unit for comparing the fourth clock signal and an output signal of the selection unit to generate the second control signal, thereby compensating an unlock error.

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First Claim