MOS Integrated test circuit using field effect transistors
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United States of America Patent
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-
Jul 13, 1982
Grant Date -
N/A
app pub date -
Feb 1, 1980
filing date -
Feb 12, 1979
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
An MOS integrated circuit arrangement with field-effect transistors includes a circuit arrangement for rapidly testing various blocks of the circuit. This circuit arrangement includes three transistor-switch groups; a first group for testing an input block, a second group for connecting and disconnecting the input block and an output block so that the blocks may be tested in combination, and a third group for testing the output block. The disclosed circuit provides a single and yet effective testing arrangement.
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