Importance

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Abstract

A memory controller method and apparatus wherein data to be written to a memory device is stored in a data queue, the data queue has a plurality of entries wherein at least two of the entries are combined to store a single datum, the single datum is wider than a single entry of the entries and addresses associated with the stored data of the data queue are stored in an address queue, thereby providing a circular write buffer. Specific memory modules of a plurality of memory modules to be refreshed are indicated to a refresh controller to thereby selectively control which of the memory modules are refreshed by the refresh controller. Access is controlled to the plurality of memory modules, each of the memory modules having an associated type. Configuration status information indicating the associated type for each of the memory modules is stored so that, if an access operation is performed to a wrong type, uncorrectable error faults are generated and can be detected. Planar data packing is performed by receiving a plurality of unpacked video data from the memory device, each of the unpacked video data having at least two channels of information, and packing the unpacked video data into packed video data by stripping at least one channel from each of the plurality of unpacked video data and then combining any remaining unstripped channel data, prior to sending the packed video data to a bus master. Planar data unpacking is performed by receiving the packed video data from the bus master, the packed video data having at least one missing channel of the at least two channels of the unpacked video data, and then expanding the packed video data to unpacked video data for storage in the memory device, thereby providing video data translation.

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First Claim