System and method for accurate negative bias temperature instability characterization
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United States of America Patent
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May 15, 2007
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app pub date -
Nov 30, 2005
filing date -
Sep 7, 2004
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Abstract
Methods and systems are provided for characterizing the negative temperature bias instability of a transistor. A bias voltage is maintained at a drain terminal of the transistor during a test period. A stress voltage is maintained at a gate terminal of the transistor during the test period, such that the stress voltage is applied concurrently with the bias voltage. At least one characteristic of the transistor is measured at periodic intervals during the stress period to determine a degradation of the at least one characteristic caused by the stress voltage until a termination event occurs.
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