Bit stream linear equalizer with AGC loop
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United States of America Patent
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Feb 16, 2010
Grant Date -
Jan 22, 2004
app pub date -
Apr 17, 2003
filing date -
Jul 22, 2002
priority date (Note) -
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Abstract
A high-speed bit stream interface module interfaces a high-speed communication media to a communication Application Specific Integrated Circuit (ASIC) via a Printed Circuit Board (PCB). The high-speed bit stream interface includes a line side interface, a board side interface, and a signal conditioning circuit. The signal conditioning circuit services each of an RX path and a TX path and includes a limiting amplifier and a clock and data recovery circuit. The signal conditioning circuit includes an AGC loop, an equalizer, and an equalizer feedback loop. The AGC loop includes a gain path and a feedback path that couples to the output of the equalizer. The equalizer feedback loop couples to the output of the equalizer and produces spectral shaping control settings that the equalizer uses to produce an equalized high-speed serial bit stream at an equalizer output.
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