Integrated circuit devices having a delay locked loop that is configurable for high-frequency operation during test and methods of operating same
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United States of America Patent
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Nov 26, 2002
Grant Date -
N/A
app pub date -
Nov 22, 2000
filing date -
Nov 23, 1999
priority date (Note) -
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status (Latency Note)
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Abstract
Integrated circuit devices and methods of operating same include a delayed locked loop (DLL) circuit that can be operated at a high frequency during a normal operation mode and during a test mode. The test mode may be, for example, for performing burn-in testing. For example, an integrated circuit device may include a DLL control circuit that generates a control signal that is responsive to a test mode signal. An oscillator circuit may generate a clock signal that is responsive to the test mode signal. This clock signal may be a high frequency clock signal, such as that used to drive a DLL circuit during a normal operation mode. A DLL circuit, which is responsive to the clock signal, may be configured to operate in either a test mode or a normal operation mode based on the control signal. By generating the clock signal at a high frequency, the DLL circuit may be evaluated during burn-in testing, for example, under conditions that are comparable to conditions during normal operation.
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