Dynamic merged load logic (MLL) and merged load memory (MLM)
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
May 15, 1984
Grant Date -
N/A
app pub date -
Dec 29, 1980
filing date -
Dec 29, 1980
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
MOS dynamic logic/shift registers employing as load elements either a parasitic bipolar transistor whose emitter is the drain of the MOS element, or the drain-substrate diode charged via bi-polar signals on the clock lines capacitively coupled to the drain. Uses for logic, memory, and imaging applications.
First Claim
Family
International Classification(s)
- [Classification Symbol]
- [Patents Count]
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully