Circuit and method for instruction controllable slew rate of bit line driver
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United States of America Patent
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-
Dec 21, 1999
Issued Date -
N/A
app pub date -
Dec 17, 1997
filing date -
Sep 27, 1996
priority date (Note) -
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status (Latency Note)
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Abstract
A bit line driver circuit includes a first driver and a second driver. The first driver drives a bit line when the bit line driver is in a first state. The second driver drives the bit line when the bit line driver is in a second state. The first driver is configured to produce a slow slew rate for the bit line and the second driver is configured to produce a faster slew rate for the bit line. The first and second drivers may include a first and second pair of driver transistors that are each coupled to the bit line. The states of the bit line driver circuit may be defined by instruction signals applied to the driver circuit and the driver circuit includes decoder logic to interface the instruction to the first and second pairs of driver transistors.
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