Semiconductor memory cell and semiconductor device
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United States of America Patent
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Oct 14, 2014
Grant Date -
Nov 29, 2012
app pub date -
Dec 15, 2011
filing date -
May 25, 2011
priority date (Note) -
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Abstract
A technology is a semiconductor cell and a semiconductor device capable of reducing the coupling capacitance between adjacent bit lines by forming a bit line junction region in a separated island shape when forming a buried bit line, thereby improving characteristics of the semiconductor devices. The semiconductor cell includes a transistor including a gate and a gate junction region, a plurality of buried bit lines disposed to intersect the gate, and a plurality of bit line junction regions, each bit line junction region having an island shape formed between the buried bit lines and connected to the buried bit line.
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