Semiconductor device
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United States of America Patent
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Jun 17, 2008
Grant Date -
Aug 3, 2006
app pub date -
Jan 11, 2006
filing date -
Jan 14, 2005
priority date (Note) -
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status (Latency Note)
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Abstract
A plurality of nonvolatile memory cells that constitute a nonvolatile memory are disposed in array form. Selection MIS.cndot.FETs for memory cell selection are electrically connected every bits. Each of the nonvolatile memory cells has a MIS.cndot.FET for writing data, a MIS.cndot.FET for reading data, and a capacitance section. Gate electrodes of the MIS.cndot.FETs and a capacitance electrode of the capacitance section are constituted of part of the same floating gate electrode. A control gate electrode of the nonvolatile memory cell is formed of part of an n well to which the capacitance electrode is opposite.
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