Clock synchronization circuit, semiconductor device, and clock synchronization method

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United States of America Patent

PATENT NO 11658665
APP PUB NO 20220321131A1
SERIAL NO

17700997

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Abstract

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A clock synchronization circuit that includes a signal generation circuit configured to generate a first signal and a second signal by receiving a signal output under a first clock with two logic circuits that respectively operate under a second clock different from the first clock; and a synchronization circuit configured to receive the first signal, the second signal, and a synchronization enabling signal for adjusting phases of the first signal and the second signal, and control the phases of the first signal and the second signal using a first output result from a logical operation performed on the second signal and on a result of a logical operation with the first signal and the synchronization enabling signal, and using a second output result from a logical operation performed on the first signal and on a result of a logical operation with the second signal and the synchronization enabling signal.

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Patent Owner(s)

  • LAPIS TECHNOLOGY CO., LTD.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Nihei, Daisuke Kanagawa, JP 1 0

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