Memory with element redundancy
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United States of America Patent
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Dec 29, 2009
Grant Date -
Jul 19, 2007
app pub date -
Feb 22, 2007
filing date -
Apr 19, 2001
priority date (Note) -
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status (Latency Note)
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Abstract
A memory device to perform an erase operation algorithm that specifically deals with different types of defects in a memory array. The memory array of one embodiment of the present invention has primary and redundant elements. A register is used for each redundant element to store the address of a defective primary element and an error code that indicates the type of defect in the defective primary element. Control circuitry is used to control memory operations to the memory array. The control circuitry performs an erase operation algorithm that is specific to an error code when a defective primary element is addressed during an erase operation.
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