Encapsulate resin LOC package and method of fabrication
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United States of America Patent
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-
May 22, 2001
Grant Date -
N/A
app pub date -
Jun 7, 1995
filing date -
Apr 29, 1994
priority date (Note) -
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status (Latency Note)
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Abstract
A method and apparatus for fabricating small form factor semiconductor chips having high temperature resistance, good humidity and chemical resistance and good dielectric properties. The semiconductor chip includes a lead frame (10) attached to an integrated circuit die (30) by a lead-on-chip (LOC) method. Wire bonds (40) are employed to connect the integrated circuit die (30) to conduction leads (75) on the lead frame (10). After the wire bonding process, the surface of the wire bonded integrated circuit is encapsulated with a layer of resin (50) using either a direct dispensing method or by a screen printing method. The encapsulated integrated circuit may then be cured and functionally tested.
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