Interruptible and restartable matrix multiplication instructions, processors, methods, and systems

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 11698787
APP PUB NO 20210326131A1
SERIAL NO

17362854

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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A processor of an aspect includes a decode unit to decode a matrix multiplication instruction. The matrix multiplication instruction is to indicate a first memory location of a first source matrix, is to indicate a second memory location of a second source matrix, and is to indicate a third memory location where a result matrix is to be stored. The processor also includes an execution unit coupled with the decode unit. The execution unit, in response to the matrix multiplication instruction, is to multiply a portion of the first and second source matrices prior to an interruption, and store a completion progress indicator in response to the interruption. The completion progress indicator to indicate an amount of progress in multiplying the first and second source matrices, and storing corresponding result data to the third memory location, that is to have been completed prior to the interruption.

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Patent Owner(s)

  • INTEL CORP.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Charney, Mark J Lexington, US 187 1309
Grochowski, Edward T San Jose, US 89 2277
Mishra, Asit K Hillsboro, US 20 273
Steely,, Jr Simon C Hudson, US 66 1208
Valentine, Robert Kiryat Tivon, IL 439 3184

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