Semiconductor memory device
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United States of America Patent
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Oct 21, 2008
Grant Date -
Jan 25, 2007
app pub date -
Jun 14, 2006
filing date -
Jul 21, 2005
priority date (Note) -
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Abstract
The present invention provides a semiconductor memory device in which the number of write amplifiers is decreased by increasing the number of bit line pairs connected to one pair of common write data lines. Further, by decreasing the number of bit line pairs connected to one pair of common read data lines, parasitic capacitance connected to the pair of common read data lines is reduced and, accordingly, time in which the potential difference between the pair of common read data lines increases is shortened. Thus, while preventing enlargement of the chip layout area, read time can be shortened.
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