Combined adder and pre-adder for high-radix multiplier circuit
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United States of America Patent
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Jun 20, 2017
Grant Date -
Sep 29, 2016
app pub date -
Mar 26, 2015
filing date -
Mar 26, 2015
priority date (Note) -
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Abstract
Circuitry accepting a first input value and a second input value, and outputting (a) a first sum involving the first input value and the second input value, and (b) a second sum involving the first input value and the second input value, includes a first adder circuit, a second adder circuit, a compressor circuit and a preprocessing stage. The first input value and the second input value are input to the first adder circuit to provide the first sum. The first input value and the second input value are input to the preprocessing stage to provide inputs to the compressor circuit, which provides first and second compressed output signals which in turn are input to the second adder circuit to provide the second sum. The preprocessing stage may include circuitry to programmably zero the first input value, so that the first sum is programmably settable to the second input value.
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