Fault diagnosis method for a sequential circuit
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United States of America Patent
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Jun 17, 1997
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N/A
app pub date -
Sep 28, 1995
filing date -
Sep 28, 1994
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Abstract
A fault diagnosis method for inferring a faulty position in an LSI includes the steps of testing the actual LSI to obtain pass/fail pin information, extracting a combinational circuit by tracing from one of a fail output pin, simulating the extracted combinational circuit using the expected outputs of flip flops located at input side of the combinational circuit as input test vectors, and inferring the faulty position by comparing the pass/fail information with the simulation results for expected values on each node in the combinational circuit for the input test vectors. The method is repeated if the faulty position is not inferred in the combinational circuit by extracting another combinational circuit preceding the combinational circuit.
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