Quantum error mitigation based on scaled gates

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United States of America Patent

PATENT NO 11928004
APP PUB NO 20230176935A1
SERIAL NO

17643206

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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Techniques regarding quantum error mitigation are provided. For example, one or more embodiments described herein can comprise a system, which can comprise a memory that can store computer executable components. The system can also comprise a processor, operably coupled to the memory, and that can execute the computer executable components stored in the memory. The computer executable components can comprise an error mitigation component that can add a set of scaled quantum gates to a quantum circuit for error mitigation. The set of scaled quantum gates can comprise a quantum gate and an inverse of the quantum gate. Also, the set of scaled quantum gates can have a rotation angle based on a pulse schedule to achieve a target stretch factor.

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Patent Owner(s)

  • IBM CORPORATION

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Earnest-Noble, Nathan Don New York, US 1 0
Egger, Daniel Josef Zurich, CH 12 29
Tornow, Caroline Zurich, CH 1 0

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