Apparatus for adaptive decoding of memory addresses
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United States of America Patent
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Jun 26, 2001
Grant Date -
N/A
app pub date -
Jun 30, 1998
filing date -
Jun 30, 1998
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Abstract
One embodiment of the present invention provides an apparatus for accessing a computer memory that bypasses decoding delays for memory type information within a memory controller. This apparatus includes a decoding circuit, for decoding a current address received from a processor to produce characteristics of a current memory module that is being accessed by the current address. These characteristics may include the size, type and speed of modules in the computer memory. The apparatus also includes a control signal generation circuit, for generating signals to control a memory access to the current address based upon the characteristics of the current memory module. The apparatus further includes a comparison module for determining whether the current address falls within a previously accessed memory module. The apparatus additionally includes a bypassing circuit. If the comparison module indicates that the current address falls within the previously accessed memory module, this bypassing circuit causes characteristics of a previously accessed memory module, obtained from a prior decoding of a previous address, to be used to generate the control signals for controlling the memory access. In a variation on this embodiment, if the comparison module indicates that the current address falls outside the previously accessed memory module, the bypassing circuit is causes characteristics of a memory module accessed by the current address to be used to generate the control signals.
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Patent Owner(s)
- ROUND ROCK RESEARCH, LLC
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Inventor(s)
Inventor Name | Address | # of filed Patents | Total Citations |
---|---|---|---|
Jeddeloh, Joseph M | Minneapolis, MN | 199 | 6220 |
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Surcharge after expiration - Late payment is unavoidable | $700.00 | $350.00 | $175.00 |
Surcharge after expiration - Late payment is unintentional | $1,640.00 | $820.00 | $410.00 |
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