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Abstract

An address for addressing a static random access memory based on a row address strobe signal, a row address, a column address strobe signal, and a column address, for addressing a dynamic random access memory, is determined by (a) latching, at a time based on the row (or column) address strobe signal, at least a portion of the row (or column) address to form latched address bits and (b) concatenating at least a portion of the column (or row) address and the latched address bits to form the address for addressing the static random access memory. A system including a static random access memory, a data bus coupled with the static random access.cndot.memory, an address bus, and a device coupled with the data bus and generating a row address strobe signal, a column address strobe signal, a row address applied to the address bus, and a column address applied to the address bus, may be provided with (a) a first address bus, coupling at least a portion of the address bus with a first portion of an address input of the static random access memory, (b) a second address bus, coupled with at least a portion of the address bus, (c) a third address bus, coupled with a second portion of the address input of the static random access memory, and (d) a latch having an input coupled with the second address bus, and an output coupled with the third address bus, and being responsive to an applied clocking signal which is based on one of the row address strobe signal and the column address strobe signal.

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First Claim