Output stage ESD protection for an integrated circuit
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United States of America Patent
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Mar 4, 2003
Grant Date -
N/A
app pub date -
Jul 26, 2000
filing date -
Jul 26, 2000
priority date (Note) -
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Abstract
An integrated circuit including a transistor having a first electrode coupled to an output bond pad and a second electrode coupled to a reference potential, such as ground bond pad. A degeneration device is coupled between the second electrode and the reference potential. A diode is coupled between the second electrode of the transistor and the reference potential with the anode of the diode coupled to the second electrode reference potential and the cathode of the diode coupled to the reference potential for an NPN transistor.
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