Low latency floating-point divider

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United States of America Patent

PATENT NO 8176111
SERIAL NO

12008785

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Abstract

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An improved method and apparatus for performing floating-point division is disclosed. In a particular embodiment, fractional operands are pre-scaled and an estimate of a reciprocal of the pre-scaled fractional divisor is obtained from a lookup table using a portion of the bits of the pre-scaled fractional divisor. This value is used to scale the fractional operands and a multiply-add operation is used based on principles of series expansion to compute a final result with an acceptable degree of accuracy.

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Patent Owner(s)

Patent OwnerAddress
ALTERA CORPORATION101 INNOVATION DRIVE SAN JOSE CA 95134

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Baeckler, Gregg William San Jose, US 75 218
Liu, Jianhua San Jose, US 358 467

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