Importance

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Abstract

A switching system for switching data with rate conversion between a high speed bus and a low speed bus, comprising a double-buffered data memory having a read-only port and a write-only port, a plurality of registers and selectors for receiving and storing successive frames of data from one of either the high speed bus or low speed bus into the data memory via one of the write-only port or said read-only port, respectively; and a connection memory containing a plurality of entries each having a first bit indicating channel ON/OFF status, an additional plurality of bits identifying connection addresses for the received frames of data; and a further plurality of index bits for addressing and reading the data memory via the other one of the write-only port or read-only port in the event the first bit is set and thereafter outputting the data to the other one of the high speed bus or low speed bus.

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First Claim