Condition bits for controlling branch processing
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United States of America Patent
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Oct 6, 2009
Grant Date -
Dec 15, 2005
app pub date -
Nov 10, 2004
filing date -
Jun 14, 2004
priority date (Note) -
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Abstract
A processing pipeline with a plurality of pipeline stages is described, with the processing pipeline comprising a front end and a back end. The processing pipeline's front end comprises an array for storing at least two condition bits, the condition bits being adapted for indicating respective conditions. The front end is adapted for resolving conditional branch instructions by accessing the array of condition bits whenever a conditional branch instruction occurs, the respective branch instruction being resolved in accordance with a corresponding condition bit. In another embodiment, the condition bits are combined with predicated execution of instructions, with the instruction's predicates being evaluated at the processing pipeline's back end.
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