Transposition circuit
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United States of America Patent
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Jun 12, 2007
Grant Date -
Sep 23, 2004
app pub date -
Jan 29, 2004
filing date -
Oct 21, 1999
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
The transposition circuit includes N input terminals (where N is an integer of 2 or greater) and N output terminals. This transposition circuit is configured such that when N packets of data for each matrix row are inputted in parallel to the corresponding input terminals, N packets of data are output in parallel for each matrix column from the corresponding output terminals. This transposition circuit generates data packets arranged as a transposed matrix and obtained from data packets in the form of an N.times.N matrix by interchanging the rows and columns of the original matrix.
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