Arrangement and method for self-synchronization data to a local clock

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United States of America Patent

PATENT NO 6604203
SERIAL NO

09394376

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Abstract

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An arrangement and a method for synchronizing data to a local clock. The invention incorporates a self-tested self-synchronous two-phase input port, wherein a line or an element of parallel data is tested for data read failure using two different phases or edges of the local clock. If a data read failure is detected using one phase, the other of the two phases is selected for reading the data. The arrangement includes a data read device for reading parallel elements of the data stream using one of two different phases or edges of the local clock, a data read error detecting device arranged to sample at least one element of the data stream using the two different phases or edges of the local clock, and a decision making device.

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Patent Owner(s)

  • ESILICON CORPORATION

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Mu, Fenghao Linkoping, SE 53 1369
Svensson, Christer Ljungsbro, SE 14 113

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