TFT with a negative substrate bias that decreases in time

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United States of America Patent

PATENT NO 6713804
APP PUB NO 20030042543A1
SERIAL NO

10199173

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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A voltage applying section (32) is connected to a silicon substrate (1). Emission of radiation to a semiconductor device causes a large number of holes to accumulate within a BOX layer (2) in the vicinity of the interface with respect to a silicon layer (3). The amount of accumulation of holes increases with a lapse of time. A voltage applying section (32) applies a negative voltage which decreases with the lapse of time to the silicon substrate (1) in order to cancel out a positive electric field resulting from the accumulated holes. The voltage applying section (32) includes a time counter (30) for detecting the lapse of time and a voltage generating section (31) connected to the silicon substrate (1) for generating a negative voltage (V1) which decreases in proportion to the lapse of time based on the result of detection (time T) carried out by the time counter (30). Consequently, a semiconductor device capable of suppressing occurrence of total dose effects is obtained.

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Patent Owner(s)

  • RENESAS ELECTRONICS CORPORATION

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Hirano, Yuuichi Tokyo, JP 65 768
Matsumoto, Takuji Tokyo, JP 134 1512
Yamaguchi, Yasuo Tokyo, JP 193 3100

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