Low leakage flip-flop circuit
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United States of America Patent
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Apr 12, 2016
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N/A
app pub date -
Jan 8, 2015
filing date -
Jan 8, 2015
priority date (Note) -
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Abstract
An integrated circuit having reduced power consumption includes a clock-gating cell, a transistor and a flip-flop. The clock-gating cell receives a dynamic enable signal, generates a latched-enable signal and gates a clock signal provided to the flip-flop. The flip-flop includes first and second latches. The transistor receives an inverted latched-enable signal from the clock-gating cell and switches ON or OFF based on the logic state of the inverted latched-enable signal. The transistor provides a voltage signal to the flip-flop circuit based on the state of the flip-flop in order to control the state of the flip-flop, which reduces power consumption of the integrated circuit.
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