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Abstract

A circuit arrangement for switching PCM channels conducting baseband data signals, with serial data to be switched arriving at n input ports and being converted in blocks to parallel form, intermediately stored in a memory and converted to serial form again after read-out to be fed to n output ports each assigned to one or a plurality of destination addresses. The parallel data blocks are intermediately stored the first time in n input registers assigned to the n input ports. Thereafter, a second intermediate storage takes place in a RAM memory in such a manner that the data blocks are written in successively according to the sequence in which they arrived at a memory address which is counted up sequentially, or the data are subsequently intermediately stored in a RAM memory at a memory address which corresponds to the respective destination address. The data blocks are read out according to the number of the output port contained in the destination address or assigned to the destination address or according to their time position and are again intermediately stored in n output registers which are assigned to the respective n output ports.

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First Claim