Importance

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Abstract

A DRAM controller (18) for controlling access to a system memory (11) is provided. Prioritizer circuit (38) causes a first plurality of buffers (42) to pass an address signal (46) for a first requesting circuit to a primary address bus (48) and a second plurality of buffers (44) to pass an address signal (46) for a next requesting circuit to a secondary address bus (50). The pages requested on primary address bus (48) and secondary address bus (50) are compared with the active page of each memory bank (11) stored in registers (52), (54), (56), and (58) by first and second plurality of comparators (60) and (70) to determine if the pages are active. The output of each of the first and second plurality of comparators (60) and (70) is coupled to a corresponding bank controller in a plurality of bank controllers (84) to produce control signals on control lines (26). A first bank decoder (80) enables an appropriate one of the plurality of bank controllers (84) to precharge an appropriate control line (26) corresponding to input from first plurality of comparators (60). The first requesting circuit signals DRAM controller (18) through a multiplexer (94) that the first requesting circuit is ready to finish accessing system memory (11) thereby allowing second bank decoder (82) to enable an appropriate one of the plurality of bank controllers (84) to precharge an appropriate control line (26) corresponding to input from second plurality of comparators (70).

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First Claim