Microprocessor for supporting reduction of program codes in size
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United States of America Patent
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Oct 12, 1999
Grant Date -
N/A
app pub date -
May 7, 1996
filing date -
May 31, 1995
priority date (Note) -
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Abstract
A microprocessor is provided for supporting reduction of codes in size, wherein instructions are extended in units of 0.5 word from a basic one word code. A word of instruction, fetched from an external memory, is transferred to a decoding register via instruction buffers and a selector both operate in units of half words, then is decoded by a decoder. A storage unit stores a state of an instruction stored in an instruction buffer. A controlling unit controls the selector so that the instructions are transferred from instruction buffers to the decoding register in units of half words based on a direction from the decoder and the states stored in the storage unit.
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