CMOS process for fabrication of ultra small or non standard size or shape semiconductor die
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United States of America Patent
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Aug 10, 2010
Grant Date -
Dec 3, 2009
app pub date -
Jun 23, 2006
filing date -
Sep 30, 2005
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Abstract
A method for the singulation of integrated circuit die, the method including: etching a semiconductor layer disposed on a silicon oxide dielectric layer, thereby forming a trench defining a boundary of the die; depositing a silicon nitride layer in the trench; coating the semiconductor layer with an oxide layer such that the trench is filled; removing part of the oxide layer from the semiconductor layer such that the oxide layer only remains in the trench; mounting the semiconductor layer to a carrier; removing the silicon oxide dialectic layer, the nitride layer, and the oxide layer; and releasing the die from the carrier. The method is suitable for irregularly shaped or extremely small die and is compatible with traditional CMOS processes.
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