Pseudo-triple-port SRAM bitcell architecture

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 11361817
APP PUB NO 20220068360A1
SERIAL NO

17002082

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Abstract

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A bitcell architecture for a pseudo-triple-port memory is provided that includes a a bitcell arranged on a semiconductor substrate, the bitcell defining a bitcell width and a bitcell height and including a first access transistor and a second access transistor. A first metal layer adjacent the semiconductor substrate is patterned to form a pair of local bit lines arranged within the bitcell width. The pair of local bit lines includes a local bit line coupled to a terminal of the first access transistor and includes a complement local bit line coupled to a terminal of the second access transistor.

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Patent Owner(s)

  • QUALCOMM INCORPORATED

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Boynapalli, Venugopal San Diego, US 36 126
Cheng, Jason San Diego, US 18 155
Gao, Yandong San Diego, US 8 26
Jung, Changho San Diego, US 75 449
Jung, Chulmin San Diego, US 102 1051
Pallerla, Arun Babu San Diego, US 19 27
Son, Sung San Jose, US 5 4

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