System and method to facilitate reset in a computer system
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United States of America Patent
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Mar 3, 2009
Grant Date -
Jan 26, 2006
app pub date -
Jul 21, 2004
filing date -
Jul 21, 2004
priority date (Note) -
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Abstract
One disclosed embodiment may comprise a computer system that includes at least one processor having at least one cache. An interface includes an associated cache, the interface preloading the associated cache with instruction data acquired from non-volatile memory as part of a reset sequence so that the instruction data in the associated cache is available to the at least one cache of the at least one processor to facilitate reset by the computer system.
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