Executing fixed point divide operations using a floating point multiply-add pipeline
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United States of America Patent
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Apr 23, 2013
Grant Date -
Nov 6, 2008
app pub date -
May 29, 2008
filing date -
Feb 10, 2005
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A mechanism for executing fixed point divide operations using a floating point multiply-add pipeline are provided. With the mechanism, the floating point execution unit in a processor is modified to include elements that may be used to perform fixed point divide operations. These additional elements include a leading zero counter, a leading one counter, an estimate table unit, and a state machine. The fixed point divide operands are converted to a floating point format and an estimate of the reciprocal of the divisor is generated using estimate tables. These values are used in multiple passes through the floating point unit for calculating estimates of the quotient and corresponding error values. The estimates of the quotient are based on previous estimates of the quotient in a prior pass through the floating point unit and a corresponding error value. The final quotient estimate is truncated.
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