Method and apparatus for scan test of SRAM for microprocessors without full scan capability
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United States of America Patent
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Apr 20, 1999
Grant Date -
N/A
app pub date -
Jun 23, 1997
filing date -
Jun 23, 1997
priority date (Note) -
Expired
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Abstract
An apparatus for allowing a RAM array within an SRAM to be tested via scan ATPG is disclosed. A first clocked flip-flop has a data input latched high, a scan-in input latched high, a clock input coupled to a signal source generating a periodic waveform, a scan-enable input coupled to a scan enable signal, and an output. The first flip-flop inverts the data input at the output when the scan enable signal is low, and places the scan-in input signal at the output when the scan enable signal is high. A second clocked flip-flop has a data input coupled to the output of the first flip-flop, a scan-in input latched high, a clock input coupled to the signal source, a scan enable input coupled to the scan enable signal, and an output. The second flip-flop inverts the data input at the output when the scan enable signal is low, and places the scan-in input signal at the output when the scan enable signal is high. A third clocked flip-flop has a third flip-flop data input coupled to an inversion of the second flip-flop output, a third flip-flop scan-in input, a clock input coupled to the signal source, a scan enable input latched low, and a third flip-flop output, the third flip-flop inverting the third flip-flop data input at the third flip-flop output. A first AND gate has a first input coupled to an inversion of the scan enable signal, a second input coupled to the second flip-flop output, and a first AND gate output. A second AND gate has a first input coupled to the first AND gate output, a second input coupled to the third flip-flop output, and a second AND gate output coupled to a write enable signal enabling the SRAM
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- 15 United States
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Patent Owner(s)
- SUN MICROSYSTEMS, INC.
International Classification(s)
Inventor(s)
Inventor Name | Address | # of filed Patents | Total Citations |
---|---|---|---|
Narayanan, Sridhar | Sunnyvale, CA | 27 | 320 |
Sanghani, Amit D | Santa Clara, CA | 9 | 43 |
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Fee | Large entity fee | small entity fee | micro entity fee |
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Surcharge after expiration - Late payment is unavoidable | $700.00 | $350.00 | $175.00 |
Surcharge after expiration - Late payment is unintentional | $1,640.00 | $820.00 | $410.00 |
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