Maximum likelihood statistical method of operations for multi-bit semiconductor memory

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United States of America Patent

PATENT NO 7480184
APP PUB NO 20080165595A1
SERIAL NO

11620704

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Abstract

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An operating procedure to provide a cost effective method to maximize the number of levels with respect to a characteristic parameter of a memory cell. The procedures utilize statistical analysis to determine the most likely binary value associated with the characteristic parameter value. In one embodiment, a receiving unit reads the values of the characteristic parameter for each memory cell in the memory cell collection containing a target memory cell. A generating unit generates a probability distribution function of the characteristic parameter for each of the possible binary values for the memory cell collection. The generating unit uses the probability distribution function to determine the probable value range for the shifted value of the characteristic parameter of the target memory cell. The value of the characteristic parameter for the target memory cell is converted into a binary value for which the probability is highest.

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Patent Owner(s)

  • GLOBALFOUNDRIES INC.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Lam, Chung H Peekskill, US 257 3524

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