Post-silicon methods for adjusting the rise/fall times of clock edges

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 6407602
SERIAL NO

10005758

Stats

ATTORNEY / AGENT: (SPONSORED)

Importance

Loading Importance Indicators... loading....

Abstract

See full text

A method for eliminating races commences with the testing of an integrated circuit for races. If a clock signal which is produced by the integrated circuit is deemed to be a cause of races, at least one transistor region is clipped from an output driver of a clock gater which produces the clock signal. The clipping is performed by reconstructing at least one mask which is used to define the output driver during fabrication of the integrated circuit. In a similar fashion, a method for increasing the rise/fall time of clock edges in an integrated circuit commences with the identification of a clock signal with a clock edge having a poor rise/fall time. The rise/fall time of such a clock edge is increased by clipping at least one transistor region from an output driver of a clock gater which produces the clock signal. Once again, the clipping is performed by reconstructing at least one mask which is used to define the output driver during fabrication of the integrated circuit.

Loading the Abstract Image... loading....

First Claim

See full text

Family

Loading Family data... loading....

Patent Owner(s)

  • HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

International Classification(s)

  • [Classification Symbol]
  • [Patents Count]

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Radjassamy, Rajakrishnan Plano, TX 11 69

Cited Art Landscape

Load Citation

Patent Citation Ranking

Forward Cite Landscape

Load Citation